As geometries in the newer semiconductor technologies become smaller and smaller, it becomes increasingly important to build redundancy (vias and contacts) into the design layouts whenever possible. Redundant via/contact structures in the design can result in improved chip reliability. Dense redundant vias have been used to provide better product yield and more robust circuit operations. Additionally, in order to prevent copper dishing, metal holes are used over large metal shapes. So there are holes in at least one of the metal layers that are interconnected by the vias. However, metal holes generated over regions of dense redundant vias can intersect the vias, degrading the circuit conductivity and performance.
In some hardware, such as 130 nm CMOS technology, some metal holes over vias have caused chip failures. In particular, some vias in the last layer (“VL”) have “punched through” the insulator below the metal holes (“MLHOLEs”) of the last thin metal layer (“ML”), touching the signal lines (ML-1) below. An example of this is shown in FIG. 6, wherein via 61 may punch through MLHOLE and the insulator and short ML-1 to circuitry above via 61. In some testsites, most macros with VLs intersecting MLHOLEs are not yieldable.
There have been proposals to remove the VLs that intersect the MLHOLEs or to remove the MLHOLEs that intersect the VLs. However, in a metal region with dense redundant vias, almost all vias, except a few peripheral vias, intersect an MLHOLE. Therefore, removing the intersecting VLs can degrade the yield or make the product less robust. Removing the intersecting MLHOLEs can lead to copper dishing.
It is therefore desirable to provide a solution that reduces the intersection of VLs and MLHOLEs without degrading product yield or robustness or increasing copper dishing. Exemplary embodiments of the present invention can provide this by mutating some of the dense redundant VLs to MLHOLEs.